OmniRouting is the first large-scale benchmark designed to evaluate LLMs on printed-circuit-board (PCB) routing reasoning under real-world industrial design-rule, manufacturability, and connectivity constraints, and reveals substantial limitations of current LMMs in PCB routing.
Abstract
Recent large language models (LLMs) have demonstrated remarkable progress in constraint-aware navigation, maze reasoning, and graph reasoning. However, their ability to reason about complex routing problems under strict geometric, topological, and electrical constraints remains largely unexplored, despite routing being one of the most challenging and critical stages of electronic design automation (EDA). To bridge this gap, we introduce OmniRouting, the first large-scale benchmark designed to evaluate LLMs on printed-circuit-board (PCB) routing reasoning under real-world industrial design-rule, manufacturability, and connectivity constraints. OmniRouting contains 1,681 industrial-grade schematic-coupled PCB designs, including board geometries, routable component placements by human engineers, footprints, pad locations, netlists, stackup information, and routing constraints. The benchmark comprises four tasks: (1) geometric routing reasoning, generating physically valid copper traces, vias, and layer assignments to connect circuit nets within constrained board regions; (2) design-rule-aware routing reasoning, producing routable layouts that satisfy clearance, trace-width, via, obstacle-avoidance, and board-boundary constraints; (3) electrical functionality reasoning, preserving schematic-specified connectivity while reasoning over net names and functional roles to produce electrically correct routing; and (4) tool-augmented agentic routing, leveraging external tools for tasks (1)-(3). Our results reveal substantial limitations of current LMMs in PCB routing, including weak path-planning capabilities, poor adherence to design-rule constraints, and inconsistent preservation of electrical functionality. We will open-source all benchmark data, evaluation code, and tool interfaces to facilitate future research.
Very Large Scale Integration (VLSI) global routing is an NP-hard combinatorial optimization problem requiring signal net assignment across capacity-constrained 3D grids while minimizing congestion, wirelength, and via transitions. Because traditional heuristics rely on static penalty schedules that fail on complex congestion topologies, we present AlphaRoute: a multi-objective adaptive search framework reformulating rip-up and reroute (R&R) into a dynamic optimization system. We introduce SHAP-based overflow decomposition to isolate per-net congestion, driving targeted subgraph extraction via 3D Dijkstra maze routing and an adaptive PathFinder policy. Crucially, AlphaRoute employs Large Language Models (LLMs) as semantic policy optimizers. Bounded by a deterministic knowledge graph, the LLMs interpret congestion metrics to dynamically adjust penalty parameters. Evaluated on ISPD 2025 benchmarks, AlphaRoute reduces overflow by 98.6% on MEMPOOL. On the constrained ARIANE design, we achieve an overflow of 146,109 (a 29.8x reduction in overflow over the state of the art), yielding a penalized score of S_orig = 0.0538 versus the State-of-the-art (SOTA) 1.780. These results demonstrate that superior algorithmic search geometry can overcome the latency of interpreted Python implementations.
Kabir Murjani, Mishri Bhavsar, Manish I. Patel et al.· arXiv.org· 0 citations
A Directed Graph-Guided Automated Algorithm Design framework, termed DGA$_2$D, which structures the open-ended program space as a directed graph, where each node represents a functional operator that can be instantiated using one of multiple candidate code implementations, while directed walks constitute complete algorithmic pipelines.
Jiale Zhao, Zi-Mu Chen, Sirui Mao et al.· 1 citation
Design-rule integration (DRI) remains a major bottleneck for scalable (Constraint Programming with SAT) CP-SAT-based standard cell synthesis and rapid technology enablement at advanced nodes. It still depends heavily on manual effort and domain expertise. Moreover, existing low-level rule encodings are not expressive enough for emerging constraints such as cut-based rules under multi-patterning technology. This paper presents \textbf{AutoDRI}, a multi-agent framework for automated design-rule integration in standard cell synthesis. AutoDRI combines a geometric semantic library, a standardized conflict-set encoding, a constructive multicolor-cut modeling method, and a feedback-driven multi-agent flow to bridge the semantic gap between natural-language design rules and executable CP-SAT constraints. In the reported experiments, AutoDRI achieves near-perfect rule-integration correctness across 41 cell benchmarks under 10+ complex rules, including colored cut-mask spacing rules, reaching 33/33 correct integrations with Gemini-3-pro and 32/33 with GPT-5.4, while maintaining runtime comparable to manual hard-coding and passing KLayout DRC and Cadence LVS.
Yuhao Ren, Yucheng Wang, Zi-Hao Chen et al.· 0 citations
Heuristic design for combinatorial optimization remains heavily reliant on expert knowledge, while existing large language model (LLM)-enhanced evolutionary methods typically evolve isolated algorithmic components, even when one determines the search state on which another operates. This paper proposes LLM-driven Heuristic Components Joint Generation (LLM-HCJG), a population-based framework that jointly generates and co-evolves interdependent heuristic components under a shared design blueprint. Applied to guided local search (GLS), LLM-HCJG couples solution initialization with penalty construction and embeds the generated pair into an enhanced online search mechanism. The resulting form is further transferred from the traveling salesman problem (TSP) to the capacitated vehicle routing problem (CVRP). Theoretical analysis establishes the non-separable state-transition effects between the two components and the advantage in generation consistency. Across synthetic instances and 41 public TSPLIB/CVRPLIB benchmarks, LLM-HCJG attains consistently low optimality gaps, including best or tied-best results on 28 of 29 TSPLIB instances and all 12 CVRPLIB instances. Ablation and structural analyses further indicate that these gains are associated with cross-component compatibility and alignment rather than isolated-component recombination. These results support effective cross-instance transfer within the evaluated routing settings under limited-sample, modest-cost training.
Junyi Wei, Yangming Zhou, Zhi-Bin Jiang et al.· 0 citations
Resource-constrained multi-object navigation in vast indoor environments ($>2,000\text{ m}^2$) poses significant challenges for efficiency and strategic planning. To tackle this, we reformulate the task as a Set Orienteering Problem (SOP), providing an optimization framework under resource constraints where exploitation is governed by the SOP model and exploration is managed by a separate heuristic switcher. Conventional baselines suffer from either rigid planning or myopic behaviors. To overcome these limitations and resolve the NP-hard computational challenges of SOP for real-time navigation, we develop the Strategic Transformer. This lightweight architecture functions as a priority planner that internalizes expert combinatorial logic into a predictable $41.03\text{ ms}$ forward pass while reducing teacher-student information asymmetry. Incorporating geometric attention biases allows the network to effectively model long-range structural dependencies. By coupling the Transformer's macro-plan with a bounded iterative 2-opt local refinement on a capped candidate graph, our framework achieves a $94\times$ speedup compared to heavy meta-heuristics, ensuring bounded-latency inference suitable for onboard deployment. Experiments on ProcTHOR validate that our method successfully bridges the gap between exploration and exploitation, outperforming carefully re-implemented baselines under Progress weighted by Path Length (PPL) and establishing a new benchmark for scalable, resource-constrained navigation.
Daiki Iwata, Kanji Tanaka, Senta Hishida· 0 citations
The topology of a routing tree determines how a multi-pin net branches and shares physical wire, directly affecting wirelength, congestion, capacitance, and delay. We study a central early-stage routing problem: minimizing wirelength while bounding the root-to-sink path stretch for every sink. SALT is the state-of-the-art constructive algorithm for this problem. We ask whether language-model-guided search can discover a constructive algorithm that improves on SALT. To make this search reliable, we develop an agent framework that combines parallel exploration with independent checking. Applied to SALT, the framework discovers a structural limitation: SALT repairs one sink path at a time and therefore never jointly decides where paths sharing root-side wire should split. This sink-local choice can split the paths too early and duplicate wire. This discovery leads to Flow-Aware Breakpoint Optimization (FABO), which jointly optimizes breakpoints across root-to-sink paths that share wire while preserving every sink's stretch budget. Across 1.29 million ICCAD15 nets and SALT's 20-point stretch-tolerance schedule, FABO reduces average FLUTE-normalized wirelength at every setting, with peak same reductions of 0.83% overall and 2.66% for nets with at least 30 pins. With 1.3x SALT's runtime, FABO-FAST identifies and optimizes most nets for which FABO provides a substantial wirelength reduction. Code is available at https://github.com/DevinShang/routing-FABO.
Shang Liu, Wenji Fang, Jing Wang et al.· 0 citations
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