Jul 2026· International Conference on Electronic Devices and Intelligent Control· Vol 14300, pp. 143001B - 143001B-6· 0 citations· 7 references
Engineering
TL;DR
A Linux kernel real-time modification scheme based on the PREEMPT_RT patch and optimizes user-space system call overhead by combining VDSO (Virtual Dynamic Shared Object) technology is proposed.
Abstract
With the increasing demand for operating system determinism in fields such as industrial automation and high-frequency trading, it is difficult for general-purpose Linux systems to meet microsecond-level control requirements due to the nonreal- time nature of their scheduling strategies. This paper proposes a Linux kernel real-time modification scheme based on the PREEMPT_RT patch and optimizes user-space system call overhead by combining VDSO (Virtual Dynamic Shared Object) technology. To overcome the limitations of pure software testing methods in terms of clock accuracy and system load interference, this paper innovatively designs a "Hardware-in-the-Loop" (HIL) latency testing method based on a PCIe interface FPGA board. This method uses the FPGA onboard 125MHz high-stability crystal oscillator as an independent time base to periodically read and verify the hardware counter through the kernel high-resolution timer, accurately quantifying the system scheduling jitter. Experimental results show that under the Fully Preemptible mode, the system's scheduling latency in multi-tasking loads is significantly reduced, meeting hard real-time application requirements.
The architecture introduces two reusable system-level design principles: interrupt-independent notification via sequence counters, avoiding OS-mediated jitter as much as possible, and cache-aware core selection based on the non-uniform cache architecture (NUCA) to reduce the variability of access latency, thereby achie...
Hui-Ji Zheng, Qing Liu, Kang Wang et al.· Electronics· 0 citations
Examination of the specific aspects of using the Linux operating system in a microprocessorbased interlocking system built on microcomputers and programmable controllers using industrial controllers with x86 architecture processors shows that the use of a standard Linux configuration is not optimal for a specialized in...
А. Т. Козлов· Transport automation researc...· 0 citations
This study proposes the design and FPGA implementation of an Optimized Pipelined RISC-V Processor, designed as a high throughput controller for Ethernet networking environment that uses a pipelined data path based on the RV32I instruction set.
S. Rao, Satish S. Bhairannawar· International journal of com...· 0 citations
The proposed architecture incorporates leakage-aware design techniques such as enable-controlled functional blocks, clock-enable based operation, and selective activation of processing modules to minimize unnecessary switching activity and reduce overall power consumption.
Embadi Thirumala, Dr B Rajanna· International Scientific Jou...· 0 citations
Results show that the proposed FIFO correctly performs read and write operations, preserves data integrity, and generates accurate full and empty flags under normal and boundary conditions, and is suitable for reliable communication between independent clock domains in digital systems.
Xiao-Xiao Li· ITM Web of Conferences· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.