Architecturale tegenmaatregelen tegen hardwareaanvallen op RISC-V-kernen

Abstract

The goal of this research is to investigate and develop embedded architectures for edge computing applications. The project targets HW/SW hybrid platforms, composed of FPGA logic coupled with embedded processors, and focuses on two aspects which are critical to IoT sensor-based settings. On the one hand, it involves the design of tailored hardware accelerators exploiting the parallel processing and hardware reconfiguration properties of FPGAs, in order to improve the performance of computationally-intensive tasks. Such tasks include signal processing or cryptographic algorithms, which are often found in edge nodes that collect and process sensor-based data. On the other hand, the project also investigates the design of processor architectures hardened against information leakage. It investigates methods to safeguard software executing in the edge platforms from adversaries aiming to break their security guarantees. The research activities will be performed around extensible processor architectures such as RISC-V. A central question is to determine the impact of the extensions in terms of cost, performance and energy consumption w.r.t. baseline designs.