Jul 2026· IEEE International Symposium on High-Performance Parallel Distributed Computing· pp. 607-608· 0 citations· 3 references
Computer Science
TL;DR
This extended abstract presents torch_cufft, a PyTorch-facing FFT system that routes FFT requests across single-GPU, single-node multi-GPU, and distributed multi-process backends, and focuses on a simple systems question: how much does the maximum feasible FFT size depend on where data lives during execution.
Abstract
Large scientific images and spectral-learning workloads often require two-dimensional Fast Fourier Transforms (2D FFTs) that exceed single-GPU memory. This matters for Fourier Neural Operators (FNOs) and Transform Once (T1)-style models, where frequency-domain computation is central to the learning workflow. PyTorch provides convenient FFT APIs, but scaling these transforms across multiple GPUs requires lower-level libraries and careful memory-layout management. This extended abstract presents torch_cufft, a PyTorch-facing FFT system that routes FFT requests across single-GPU, single-node multi-GPU, and distributed multi-process backends. We focus on a simple systems question: how much does the maximum feasible FFT size depend on where data lives during execution? In single-node capacity experiments, descriptor-resident cuFFTXt execution extends the 2D FFT frontier beyond both single-GPU PyTorch and integrated sharded XT execution, reaching 74752 × 74752 on 4 × V100 and 88064 × 88064 on 4 × L40S while preserving FP32-scale correctness in validated configurations.
DataKernelBench is introduced, which translates SQL into validated PyTorch TorchPlan programs and evaluates LLMs that optimize either the core tensor-bounded snippet or the full query in CUDA or Triton through execution-guided repair and finds that higher-performing implementations commonly use kernel fusion and execut...
Celty, a co-designed sparse format, GPU kernel, and SIMT microarchitecture for efficient spMspV in LLM inference is proposed, which introduces a Run-Length Compressed CSC format that enables vectorized loading of compressed weight columns and exploits both sparsity sources to skip unnecessary memory accesses.
SA-Scheduler is presented, a structure-derived bottleneck-aware scheduling framework for multitasking MCM-GPUs that determines chip placement without hardware modification or runtime bottleneck profiling, and provides a principled and scalable foundation for multitasking on future MCM-GPUs.
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