Jul 2026· IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies· pp. 297-302· 0 citations· 17 references
Abstract
Securing memory in resource-constrained embedded systems remains a critical challenge due to the susceptibility of statically stored cryptographic keys to physical and sidechannel attacks. This paper presents a lightweight memory obfuscation architecture based on Physical Unclonable Functions (PUFs), utilizing the intrinsic manufacturing variations of Arbiter PUFs (APUFs) to generate device-specific encryption keys dynamically at runtime, thereby eliminating the need for persistent key storage. The proposed system employs a hardware-rooted XOR-based encryption scheme in which memory addresses are transformed into challenges to produce unique, non-stored keystreams for memory protection. The architecture is implemented on an FPGA platform using a MicroBlaze-based system, integrating a custom XOR encryption engine and a finite state machine (FSM) for secure access control and device authentication. Experimental results demonstrate strong statistical security properties, with ciphertext achieving near-ideal entropy (7.9987 bits/byte), negligible correlation with plaintext, and a uniform distribution under chi-square testing. Furthermore, the design exhibits low hardware overhead, utilizing only 3.15% of LUT resources and consuming 0.235 W, highlighting its suitability for IoT and resource-constrained applications. These results confirm that PUF-based dynamic key generation combined with lightweight XOR encryption provides an effective and efficient hardware-rooted solution for memory protection.
With lightweight hardware security becoming increasingly critical for Internet of Things devices, Physical Unclonable Functions (PUFs) have emerged as a key enabling technology, providing device authentication, cryptographic key generation, and simplified key management capabilities without requiring dedicated on-chip...
Peizhen Hong, Zhixin Ren, Gui-Qin Li et al.· International Journal of Inf...· 0 citations
Cryptographic accelerators implemented on Field-Programmable Gate Arrays (FPGAs) are highly vulnerable to bitstream-level fault injection attacks. However, executing spatially precise attacks on undocumented, proprietary bitstreams remains a significant reverse-engineering challenge. In this paper, we propose a novel,...
Christopher Josiah Stance, Mani Rupak Gurram, D. Idowu et al.· National Aerospace and Elect...· 0 citations
Memristor-based hardware security primitives have attracted attention owing to their intrinsic variability and stochastic switching dynamics; however, most prior demonstrations implement physical unclonable functions (PUFs), true random number generators (TRNGs), and cryptographic operations as functionally separated m...
Function secret sharing (FSS) is a core building block for privacy-preserving systems such as secure inference and private information retrieval (PIR), but incurs significant overhead in key generation, communication, and data movement.We present the distributed function accelerator (DFA), a hardware accelerator that t...
The Secure Hardware Extension (SHE) provides crucial functionalities such as error-detection, authorization, and authentication of messages exchanged between Electronic Control Units (ECUs) over the Controller Area Network (CAN) bus with the help of Advanced Encryption Standard (AES) cryptographic cores. However, the s...
Soumi Chatterjee, Siddhartha Chowdhury, Urbi Chatterjee et al.· ACM Transactions on Embedded...· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.