Jul 2026· 2026 IEEE International Conference on Quantum Software (QSW)· pp. 129-140· 2 citations· 40 references
Abstract
Modern High-Performance Computing (HPC) infrastructures are increasingly integrating multiple Quantum Processing Units (QPUs) of different types alongside classical resources. Unlike traditional accelerator scheduling, quantum device selection affects not only performance but also the quality of the computed result because current quantum hardware exhibits device-dependent noise characteristics. This makes efficient and fidelity-based device selection a key challenge in multi-QPU environments. In this work, we propose a Graph Neural Network (GNN) model that exploits the structural representation of quantum circuits to predict their execution fidelity across different QPUs. By operating on uncompiled circuits, the approach supports earlystage device selection and enables making informed scheduling decisions. We evaluate the model on a diverse set of benchmark circuits compiled for superconducting and trapped-ion devices. The results show that the proposed approach outperforms existing baseline models, achieving 30% Mean Squared Error (MSE) and 20% Mean Absolute Error (MAE) reduction, and provides an effective basis for fidelity-based scheduling in heterogeneous HPC-quantum systems.
High Performance Computing-Quantum Computing (HPCQC) platforms expose multiple Quantum Processing Units (QPUs) that may differ in size, topology, native gates, and noise characteristics. For current noisy devices, errors compound along the compiled circuits quickly, and minimizing them, that is, maximizing the circuits'execution fidelity, is essential for reliable results. Fidelity depends on the compilation to a specific target device: the same high-level circuit may produce different executables and, therefore, different expected fidelities across QPUs. We present a low-overhead fidelity-aware scheduling framework for multi-QPU systems based on a Graph Neural Network (GNN) that estimates, before compilation, the expected fidelity of each circuit on each available QPU. Then, a tunable scheduler uses these estimates to control the trade-off between execution fidelity and parallelism. Results show that this framework allows for approximating an exhaustive fidelity-based assignment, saving computational resources compared to a brute-force approach that compiles each circuit on every device.
Innocenzo Fulginiti, Antonio Tudisco, Salvatore Zammuto et al.· 0 citations
Hybrid Variational Quantum Algorithms (VQAs) present a highly viable pathway to near-term quantum utility; however, their performance is fundamentally bottlenecked by classical-quantum communication latency in Quantumas-a-Service (QaaS) environments.
This paper proposes an optimized classical-quantum orchestration architecture designed to minimize cloud-induced latency and maximize Quantum Processing Unit (QPU) active compute time. By implementing edge-colocated classical optimizers alongside batched parameter-shift gradient evaluations, the system circumvents stateless cloud API barriers.
Benchmarking across parameterized quantum circuits ranging from 15 to 50 qubits demonstrates an 84% reduction in network-induced QPU idle time. The framework yields a 3.2 × speedup in overall convergence time for the Quantum Approximate Optimization Algorithm (QAOA) and up to a 98% reduction in classical API call overhead compared to standard RESTful QaaS execution models.
These quantitative findings demonstrate that tightly coupled hybrid co-processing, physically adjacent to the control electronics, is critical for extending the computational bound of Noisy Intermediate-Scale Quantum (NISQ) devices.
Akshay Joseph, R. Delhibabu· Frontiers of Computer Scienc...· 0 citations
Predicting the runtime of noisy quantum circuit simulations is important for scheduling, resource allocation, and performance optimization. However, accurate prediction is challenging because backend-aware transpilation can substantially alter the original circuit structure, while the backend-derived noise model and simulator execution behavior can introduce additional runtime variation. We study the effectiveness of graph neural networks (GNNs) and conventional regression methods in predicting Qiskit Aer simulation runtime measured after transpilation. We construct a dataset from a benchmark pool of 1,402 unique circuits spanning 22 circuit families, two Qiskit fake-backend configurations, and four transpiler optimization levels. Specifically, we compare a source GNN using original circuit information, hybrid GNN combining source-level graph with post-transpilation features, and transpiled GNN using only transpiled circuit information, along with five regression models. In the overall-model setting, the transpiled GNN achieves the strongest performance among the graph-based representations at all four optimization levels, obtaining $R^2$ values of 0.974, 0.713, 0.745, and 0.605 for optimization levels 0 through 3, respectively. However, under backend-specific evaluation, the advantage of GNN decreases, with conventional regression models matching or outperforming the GNNs in several settings. These results indicate that post-transpilation information is useful, while the value of explicit graph modeling depends on the backend and optimization level.
Davud Azizov, Javier Vela-Tambo, Tian Guo· 0 citations
As quantum processors scale to hundreds of qubits, execution speed is a critical performance dimension alongside scale and quality. While substantial progress has been made in benchmarking circuit fidelity, existing speed metrics often fail to reflect the sustained, end-to-end throughput experienced by users running utility-scale workloads. This shortfall is especially pronounced for layered, parameterized circuits executed repeatedly within classical-quantum workflows, such as variational algorithms and error-mitigated simulations. In this work, we formalize CLOPS_h (Circuit Layer Operations Per Second) as a holistic speed benchmark defined over layered, hardware-aware circuits. CLOPS_h measures the sustained rate at which the system executes physical layers, parallel slices of qubit-disjoint two-qubit gates separated by synchronization barriers. Because each such layer is one time slice of an N-qubit circuit, this rate maps directly to the execution rate of layered $N$-qubit circuits, connecting CLOPS_h to published device capability claims, and to the device-level throughput ceiling we formalize as Max Circuits Per Second (MCPS). CLOPS_h is obtained under layer-fidelity operating conditions, binding the speed measurement to an independently verified quality envelope, and it shares its layer decomposition with scalable layer-fidelity (LF) quality benchmarks, enabling coherent interpretation of speed and quality without conflating the two.
Analog quantum processors based on Rydberg atom arrays are a powerful platform for many-body quantum simulation, combinatorial optimization, and graph machine learning. As these devices become increasingly accessible, establishing confidence in their outputs requires predictive models that quantitatively connect microscopic hardware imperfections to empirical results. Here, we present a noise-aware emulation framework that propagates the dominant noise mechanisms throughout the full computation cycle to predict device behavior. We validate the framework by benchmarking two representative protocols, quantum annealing and post-quench dynamics, on three Pasqal quantum processors where classical simulations still provide ground truth. Across all three devices, the measured observables fall within the uncertainty envelopes predicted by the emulator. Beyond reproducing the data, the framework isolates which physical mechanism dominates in each operating regime, provides quantitative guidance for algorithm design and hardware improvements, and establishes a foundation for verifying analog processors in regimes beyond classical reach.
Constantin Dalyac, Sergi Julia-Farr'e, L. Leclerc et al.· 3 citations· ⚡1
A novel physics-guided linear mapper for quantum error mitigation that uses seven distinct interpretable features derived from circuit complexity and device calibration data, which reveals that circuit depth and CNOT count dominate error prediction, consistent with decoherence mechanisms.
Tulsi Chaudhari, Krish Bhatia, Shalini Devendrababu et al.· Lecture Notes in Networks an...· 0 citations
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