Design and Implementation of RISC-V SoC with Memorymapped Neural Network on Caravel
Abstract
Edge-AI systems for fluorescence spectrum classification require low-latency inference and efficient hardware integration to support real-time environmental monitoring. This paper presents the design and implementation of a RISC-V based system-on-chip (SoC) with a memorymapped neural network accelerator (NNA) on Caravel. The proposed architecture employs a softcore RISC-V processor to control a fixed-point feedforward neural network accelerator through a Wishbone/MMIO interface, enabling modular integration without modifying the processor pipeline. The accelerator performs multiply-accumulate, activation, and argmax-based classification using quantized parameters stored in hardware-compatible memory files. Design verification is carried out through RTL simulation and Caravel-oriented MMIO validation, including register write, inference triggering, and readback of status, output class, and cycle count. Simulation results show 50 passing samples with zero mismatch and an inference latency of 21 clock cycles. The design is also evaluated using the OpenLane ASIC flow, which produces hardened macro outputs and wrapper-level integration, demonstrating physical implementability. The proposed system provides a practical and scalable approach for integrating dedicated neural network hardware into an open RISC-V SoC platform.