This project developed an FPGA-accelerated matrix multiplication system on the PYNQ-Z2 platform to address the challenge of performing tiled large-matrix computation under tight memory, communication, and hardware resource constraints and demonstrated that full-stack measurement can guide more effective FPGA optimization than hardware-only tuning.
The rapid advancement of quantum computing severely threatens conventional public-key infrastructure, promoting the migration to Post-Quantum Cryptography (PQC). With NIST standardizing Module-Lattice-Based Digital Signature Algorithm (ML-DSA) as FIPS 204, the high computational complexity of lattice-based cryptography...
Xiao Liu, Qing-Xin Xie, Hui-Hong Zhang et al.· International Test Conferenc...· 0 citations
This research presents an optimized, reduced-clock-cycle approach for performing 128-bit floating-point calculations on Field-Programmable Gate Arrays (FPGAs) using the SRMA architecture, which not only reduces execution time but also decreases energy consumption on Kintex-7 FPGA boards.
N. P, Thirumalaiswamy V., H. S. et al.· International Journal of Com...· 0 citations
Modern systems-on-chip (SoCs) rely on heterogeneous accelerators for performance scaling. Memory access is a critical bottleneck, but the complexity of cache coherence and nuances of weak memory consistency models (which may vary from system to system) represent a significant designer burden to every load/store unit th...
Joseph Maheshe, G. Lemieux· IEEE International Conferenc...· 3 citations
Dilithium is a lattice-based digital signature scheme selected in the post-quantum cryptography (PQC) standardization process by the National Institute of Standards and Technology (NIST). To address the inefficiency issue, a targeted acceleration scheme for Dilithium is designed by combining the hardware characteristic...
Wei-Cheng Hu, Jun-Jie Zhong, Tian-Ming Gao et al.· International Test Conferenc...· 0 citations
Complex scalar kernels often contain instruction fragments whose computation is simple but whose operand demand exceeds the traditional two-input–one-output custom-instruction model. This operand interface bottleneck limits instruction merging in tightly coupled RISC-V acceleration. This paper proposes a multi-operand...
Peng Lu, Mei-Jiao Yu, You-Ping Mao et al.· Electronics· 0 citations
The architecture introduces two reusable system-level design principles: interrupt-independent notification via sequence counters, avoiding OS-mediated jitter as much as possible, and cache-aware core selection based on the non-uniform cache architecture (NUCA) to reduce the variability of access latency, thereby achie...
Hui-Ji Zheng, Qing Liu, Kang Wang et al.· Electronics· 0 citations
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