Jul 2026· AI Engineering· Vol 2· 0 citations· 23 references
TL;DR
This paper will review different research tasks and display tables of hardware efficiency and wireless system metrics, and reviews three critical categories of processing chips: Neuromorphic chips, Neural Processing Units (NPUs), and Tensor Processing Units (TPUs).
Abstract
The introduction of 6G Networks and its deep integration of Artificial Intelligence (AI) necessitates powerful and efficient hardware processors to manage massive data flows, ensure network reliability, and support demanding use cases. To overcome these challenges, the industry is shifting away from conventional processing architectures (CPUs and GPUs) toward specialized hardware accelerators. This paper reviews three critical categories of processing chips: Neuromorphic chips, Neural Processing Units (NPUs), and Tensor Processing Units (TPUs). It also reviews other emerging chips that are still relatively unknown such as Quantum Processing Units (QPUs) and Photonic Integrated Circuits (PICs). Specifically, this paper will review different research tasks and display tables of hardware efficiency and wireless system metrics.
This survey reviews 71 studies published between 2015 and 2025 and organizes them into a taxonomy that classifies GPU works into simulation frameworks, training-acceleration techniques, large-scale and multi-GPU simulation, and application deployments, and RISC-V works into instruction-set extensions and tightly-couple...
Edris Zaman Farsa, Amirhossein Ilkhani, Marc Reichenbach et al.· Neuromorphic Computing and E...· 0 citations
Conventional processors face fundamental bottlenecks when deployed in resource‑constrained aerospace systems that demand onboard intelligence. This review examines brain‑inspired neuromorphic computing as an alternative, focusing on digital neuromorphic processors with embedded central processing unit (CPU) control, mu...
Yi Zhong, Tao Zhang, Jin-Hao Ruan et al.· Hyper· 0 citations
The view taken here is that brain-inspired computing is heading toward a hybrid future: conventional digital processors will keep doing what they do best, while event-driven and in-memory accelerators take over the workloads where they have a genuine edge.
Jisna C. Jeejo, Habeeba M. A.· International Journal of Tec...· 0 citations
A comparative discussion is offered between integrated programmable architectures and physically adaptive, self-organized systems, identifying the key open challenges: scalability, stability, training efficiency, standardized benchmarking, and the integration of memory and computation, together with the opportunities t...
The rapid expansion of artificial intelligence (AI) into edge devices, autonomous systems, intelligent sensors, robotics, healthcare platforms, and pervasive Internet-of-Things environments has exposed fundamental limitations in conventional computing architectures. Although contemporary deep neural networks achieve re...
Naveen Kumar, Achyutanand Mishra, Ravi Ranjan et al.· International Journal of Res...· 0 citations
An adaptive pruning convolutional neural network (APCNN) based on Si-based ferroelectric ambipolar field-effect transistor (Fe-AmFET) crossbar arrays is demonstrated, achieving an ultrahigh kernel pruning ratio with negligible accuracy degradation on the Fashion-MNIST dataset.
Yusen Tian, Penghao Chen, Ziyu Ming et al.· National Science Review· 0 citations
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