A Resolution-Adaptive Hardware Architecture for Real-Time Sobel Edge Detection, Achieving Sub-Linear Resource Scaling.

Abstract

Edge detection is a key area within computer vision, and it has become an integral part of various application areas. Edge detection enables the identification of edges, which are critical features in images and represent important attributes that help in extracting key and distinguishing information from the images. The hardware implementation of edge detection must be fast, should use minimal resources, consume less power, and must be adaptable to different image resolutions. This paper implements Sobel edge detection for adaptive image resolution, ranging from a low-resolution image to full high-definition, and uses a modern heterogeneous Field Programmable Gate Array (FPGA) platform, the Ultra96-V2. The results reveal that only 5% of the FPGA on-board resources, including the Look up Tables (LUTs), Flip Flops (FF), Digital Signal Processor (DSP), and Block Memory (BRAM), are utilized for low resolution images, while approximately 23% of the onboard resources are consumed for high resolution images. This demonstrates that the increase in resource utilization when transitioning from low resolution to high resolution images is less than 20%. Additionally, the power dissipation is approximately 2 W for the highest resolution, and the maximum operational frequency is recorded at 136 MHz for high resolution and 166 MHz for low resolution images, showing only 18% decrease in the frequency. The proposed architecture achieves sub-linear resource scaling, with less than 20% increase in resource utilization and less than 20% reduction in speed and power when handling a 56-fold increase in pixel count, leveraging the advantages of modern heterogeneous FPGA architecture. Consequently, the adaptive resolution capability combined with low resource scaling makes the proposed design particularly suitable for real-time edge detection applications demanding high-quality image processing.