Jul 2025· IEEE Journal on Exploratory Solid-State Computational Devices and Circuits· Vol 12, pp. 176-184· 3 citations· 28 references
Computer Science
TL;DR
A3D-MoE addresses large language models' challenges with 3-D heterogeneous integration to improve memory bandwidth and reduce NoC overhead/energy, and a hardware resource-aware operation fusion scheduler that fuses attention/MoE operations to boost performance.
Abstract
Conventional large language models (LLMs) have large parameter sets, making inference costly and energy-intensive; mixture-of-experts (MoEs) mitigates this by activating fewer weights per token, but fine-grained MoE LLMs still face runtime workload variability, inefficient conventional scheduling, and high bandwidth memory (HBM) loading energy/bandwidth demands. A3D-MoE addresses these with 3-D heterogeneous integration to improve memory bandwidth and reduce NoC overhead/energy; a 3-D-systolic array with V-Cache reuse and unified 3-D dataflow to optimize hardware utilization across workloads; a hardware resource-aware operation fusion scheduler (HR-OFS) that fuses attention/MoE operations to boost performance; and MoE Score-Aware HBM access reduction with even–odd expert placement (MoE-HBMR-EOP) to reduce HBM access/bandwidth demand. Evaluations show <inline-formula> <tex-math notation="LaTeX">$1.8\times $ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> lower latency, <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> lower energy, and <inline-formula> <tex-math notation="LaTeX">$1.44\times $ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">$1.8\times $ </tex-math></inline-formula> higher throughput than the state-of-the-art.
ThAME is proposed, a three-dimensional (3D) heterogeneous multi-chiplet architecture for MoE inference that employs Ferroelectric Field-Effect Transistor-based non-volatile and DRAM-based volatile memory chiplets with a co-designed compute mapping strategy that aligns the distinct computational profiles of attention me...
Pratyush Dhingra, Pramit Kumar Pal, J. Doppa et al.· arXiv.org· 0 citations
EPIC mitigates imbalance via performance-aware expert migration and runtime expert activation, and then improves communication with topology-adaptive transport kernels and fine-grained computation-communication overlap.
Jia-Min Cao, Qingxu Li, Yaozhong Liu et al.· Conference on Applications,...· 2 citations· ⚡1
A ReRAM near-memory architecture that keeps expert weights resident behind high-bandwidth local reads and recovers occupancy with bounded core-local multicast pooling, coactivation-aware placement, and load-aware fetch, and sizes each communication level from induced demand is presented.
Kun-Ming Shao, Ming Zeng, Xin Yuan et al.· 0 citations
This work explores an HBF organization that simultaneously exploits two independent expert-delivery routes: a direct path that transfers expert weights from HBF to the GPU and a relay path that transfers them from HBF through the HBM base die to the GPU.
Seeyeon Kim, Juhyeong Jin, Joo-Young Kim· 4 citations
Results show that compact SLMs paired with PEFT provide a practical, energy-aware path to personalized on-device deployment, with the optimal method set by the dominant constraint: LoRA+ for energy and QLoRA for memory.
NoVA is proposed, a technology-architecture co-designed NMP system that overcomes both walls and achieves on average 4.5x higher throughput, 69.8% lower end-to-end latency, and 5x better energy efficiency over a GPU baseline, with only 3.9% area overhead and no loss in memory capacity.
In Jung, Jaeha Min, Joo-Young Kim· 0 citations
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