Hardware-Assisted Spatial Memory Safety for Shared GPU Accelerators: A Pointer Tagging Co-Design with Analytical and Synthesis-Level Evaluation
TL;DR
This work presents a hardware–software co-design whose 16-bit tag uses odd parity and fail-safe class encoding, which combines a variable-precision extent, an aligned CRC checker, and an exact-bounds micro-cache.
Abstract
Graphics processing units (GPUs) underpin high-performance computing, but device partitioning does not ensure that an in-context pointer remains within its allocation. We present a hardware–software co-design whose 16-bit tag uses odd parity and fail-safe class encoding. It combines a variable-precision extent, an aligned CRC checker, and an exact-bounds micro-cache. For 200,000 log-uniform requests from 16 B to 1 TiB, mean Class 4 fragmentation is 1.638%, versus 27.733% for power-of-two encoding. The seven-bit aligned signature has full GF(2) rank and a 1/128 non-adaptive collision rate; its deterministic window is exactly one through three regions and tight at four. Exhaustive testing rejects every one-bit tag corruption, while two-bit analysis demonstrates why parity is not adversarial authentication. A SAT-equivalent endpoint rewrite reduces Class 3 generic depth from 60 to 24 levels. A fail-closed 32-lane Class 4 topology detects nonuniform active-lane tags in hardware; for uniform tags, it reduces generic CMOS cost from 155,200 to 72,872 transistor equivalents (53.05%) and depth from 67 to 61 levels. Official SASS traces provide an analytical exposure bound rather than native simulation; a separate pre-layout 45 nm mapping is reported only as a timing sensitivity experiment.
