Analysis of Research Progress on Deployment Methods for Deep Learning Models on FPGAs

Abstract

Deep learning (DL) models have achieved remarkable progress in natural language processing, computer vision, content generation, and edge intelligence; however, their rapidly increasing computational complexity, memory demand, and deployment diversity pose significant challenges for practical implementation. Field-programmable gate arrays (FPGAs) provide customized low-precision computation, spatial dataflow, on-chip data reuse, reconfigurability, and rich I/O capabilities, making them an important platform for DL inference. This paper presents a systematic review of FPGA-based DL deployment from a cross-layer perspective spanning model, compiler, architecture, runtime, and electronic design automation (EDA). Following a PRISMA-guided evidence synthesis protocol, this review analyzes DL workload characteristics, FPGA architectural optimizations, deployment toolflows, and physical implementation challenges. A unified taxonomy is proposed along the specialization–programmability continuum, including model-fixed accelerators, generator-based accelerators, template-configurable accelerators, and ISA-programmable overlays. These approaches are compared according to hardware regeneration requirements, model adaptability, operator coverage, compilation cost, and deployment flexibility. Furthermore, emerging workloads, including vision Transformers, graph neural networks, large language models, and multimodal models, are analyzed from the perspectives of computation, memory behavior, and runtime coordination. The review shows that FPGA deployment efficiency increasingly depends on memory capacity, mutable state management, operator support, and end-to-end compilation capability rather than peak multiply–accumulate throughput alone. Based on the analysis of 70 primary FPGA implementation studies, this paper highlights that reliable cross-study comparison requires careful consideration of model configuration, precision, execution phase, batch size, memory residency, FPGA platform, and evidence maturity. For multimodal generative models, the current evidence remains limited, with no identified end-to-end FPGA-based vision–language model implementation in the reviewed corpus. This review provides a systematic perspective for future FPGA-based DL deployment research, emphasizing cross-layer optimization, physically aware compilation, extensible accelerator architectures, and practical deployment efficiency.