2026· Journal of Advances in Information Technology· Vol 17, pp. 1442-1455· 0 citations· 27 references
TL;DR
A framework for parallel divide-and-conquer algorithms that separates the performance contributions of algorithmic structure from those of the underlying runtime, and introduces hardware-aware threshold selection for Intel’s hybrid P-core/E-core architecture.
Abstract
—We present a framework for parallel divide-and-conquer algorithms that separates the performance contributions of algorithmic structure from those of the underlying runtime. The framework implements true recursive parallel decomposition via rayon::join() at every recursion level—explicitly contrasted with wrapper approaches that delegate to opaque library routines—and introduces hardware-aware threshold selection for Intel’s hybrid P-core/E-core architecture. We formalize algorithm behavior using the work-span model and derive closed-form expressions for the serial fraction that governs scalability. On the i7-13650HX (6 P-cores + 8 E-cores), parallel merge sort achieves 6.35× speedup at 1M elements, while Amdahl’s-law analysis attributes the 39% efficiency ceiling at 14 cores to a 13% inherently sequential merge fraction—a structural bottleneck distinct from runtime overhead. Thread affinity experiments show P-core-only placement outperforms all-core Operating Systems ( OS ) scheduling by 14% for quicksort. Honest benchmarking against Rust’s standard library, Rayon, ndarray, and Intel Math Kernel Library (MKL) confirms that production libraries achieve 3–30× superior throughput through combined pdqsort, Single Instruction Multiple Data (SIMD), and Basic Linear Algebra Subprograms (BLAS) optimizations, while our framework isolates individual optimization layers for research. The complete framework is released as open-source software under the Massachusetts Institute of Technology (MIT) license to support reproducible research.
A high-performance SIMD acceleration framework for the Steinhaus-Johnson-Trotter algorithm, targeted at modern x86-64 architectures using the AVX2 instruction set, extended into a highly concurrent environment via OpenMP using a localized mathematical state decoder and macro-period loop scheduling.
This paper presents TopSim, an extensible C++ framework for developing numerical simulations in parallel and distributed environments. The framework’s contribution is architectural rather than algorithmic, arising from the integration of three key architectural features within a unified execution model: (1) a service-o...
Leonardo S. Duarte, Rodrigo Espinha, H. Goicoechea et al.· Journal of the Brazilian Soc...· 0 citations
Loom, a tuning-free symbolic compiler framework for tile-based SPMD programs on spatial dataflow architectures, is presented, suggesting that hardware-derived symbolic compilation provides a retargetable alternative to profiling-based tuning for spatial dataflow architectures while remaining interpretable by keeping op...
He-Ru Wang, Wei Li, Zhen-Yu Bai et al.· 0 citations
This study extends the five-algorithm benchmark of Wibowo and Faisal [12] — which compared Heap, Shell, Merge, and Quick Sort against Python's built-in Timsort — to a twelve-algorithm framework spanning comparison-based, non-comparison-based, and hybrid/adaptive paradigms. Execution time (time.perf_counter()) and peak...
B. Mit· International Journal of Lat...· 0 citations
The increasing diversity of parallel hardware challenges existing compilation flows. While OpenMP provides a portable abstraction for shared-memory parallelism, existing compilers tightly couple the frontend semantics with fixed lowering strategies. This design limits performance portability across different runtimes a...
Luca Parigi, Giuseppe Tagliavini· 0 citations
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