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Sep 2026
TierSizer: Counterfactual Reasoning for DRAM Sizing in Tiered Memory Systems
Compute Express Link (CXL) enables cost-effective memory capacity expansion by placing additional tiers behind a coherent fabric. To overcome the performance loss induced by the higher latency of CXL, tiering systems keep hot data in DRAM and demote cold data to the slower tiers. While most research has focused on the...
Sujay Yadalam, Saarth Deshpande, Divyanshu Saxena et al.
· Proceedings of the 4th Works... · 0 citations