TierSizer: Counterfactual Reasoning for DRAM Sizing in Tiered Memory Systems

Abstract

Compute Express Link (CXL) enables cost-effective memory capacity expansion by placing additional tiers behind a coherent fabric. To overcome the performance loss induced by the higher latency of CXL, tiering systems keep hot data in DRAM and demote cold data to the slower tiers. While most research has focused on the data placement problem, very little addresses the basic operational question: how much DRAM does an application actually need to meet a performance target on a tiered system? Too much DRAM wastes the savings that motivated tiering; too little degrades performance. The right size is workload-dependent and drifts over time, so operators today over-provision conservatively or accept silent slowdowns. We observe that sizing DRAM requires predicting an application's slowdown at different DRAM sizes — a counterfactual that must be answered while the workload runs, without instantiating the size. We show this counterfactual is answerable online from commodity system metrics using two simple analytical models, one for the change in LLC-miss stalls and one for migration overhead. Both models account for a real, imperfect tiering engine rather than an idealized one. We build TierSizer, an online predictor and controller that steps DRAM toward its minimum, in small increments, keeping performance within a target and avoiding tail-latency spikes. On a diverse set of workloads atop a state-of-the-art tiering system, TierSizer saves 35% DRAM on average (up to 90%) over a 2:1 configuration while staying within 5% of baseline performance.