Ajay Kumar

A Multi-Frequency Performance Evaluation of an 8-Bit Fixed-Bias Truncated Approximate Multiplier Design on FPGA

An RTL-to-FPGA design and implementation analysis for an 8-bit fixed-bias truncated approximate multiplier has been evaluated on the XC7Z020-CLG484-1 device fabricated at 28 nm. The main central approximate core eliminates partial-product columns 0–5 (CUT=6) and inserts the corrected column C_FB=2^6=64 at the first res...