A Multi-Frequency Performance Evaluation of an 8-Bit Fixed-Bias Truncated Approximate Multiplier Design on FPGA

Abstract

An RTL-to-FPGA design and implementation analysis for an 8-bit fixed-bias truncated approximate multiplier has been evaluated on the XC7Z020-CLG484-1 device fabricated at 28 nm. The main central approximate core eliminates partial-product columns 0–5 (CUT=6) and inserts the corrected column C_FB=2^6=64 at the first reserved column. To observe the different architectural sound effects, both the exact and fixed-bias cores are evaluated with isolation at same input/core/output register boundaries, FPGA target for synthesis and implementation settings, clock constraints, and fabric-only DSP policy. A fully comprehensive evaluation of all 65,536 unsigned 8-bit test cases have been run for simulation and verification. A vast range of targets from 50 to 200 MHz are analyzed for observing post-route timing. The obtained results at 200 MHz reveal that, in case of the fixed-bias model structure reported +0.012 ns WNS while in the exact reference was −0.132 ns, LUT utilization was 68 versus 84 LUTs respectively, and consumes 0.021 versus 0.029 W dynamic power in fixed bias versus exact reference respectively. The study state that the PDP values decreases from 0.1488 to 0.1047 nJ and LUT-based ADP from 431.09 to 339.18 LUT•ns respectively. During the evaluation across the full sweep, the average changes reported in the fixed bias and exact reference models are 27.4% in dynamic power, 21.1% in LUT count, 28.0% in PDP, and 21.7% in ADP.