Author

Andrew Boutros

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Sep 2026

FPGA Architectures to Enable Concurrent LUT and Adder Chain Usage

Flexibility and customization make Field-Programmable Gate Arrays (FPGAs) attractive for arbitrary-precision arithmetic-heavy workloads such as sparse and mixed-precision DNN inference. However, in modern logic blocks, the hardware adder chain is typically driven only by look-up table (LUT) outputs, preventing adders a...

Xilai Dai, Junius Pun, Anthony Fei et al. · ACM Transactions on Reconfig... · 0 citations

Preprint Jul 2026

From Patterns to Parsers: Automatic Generation of Efficient Hardware Parsers for FPGAs

This work presents an open-source tool for automatically generating efficient hardware parsers from high-level specifications. It uses a parsing intermediate representation (PIR) that decouples application-specific frontends from a common register-transfer level (RTL) generation backend. The backend produces optimized,...

Tushar Garg, Andrew Boutros · 0 citations