FPGA Architectures to Enable Concurrent LUT and Adder Chain Usage

Abstract

Flexibility and customization make Field-Programmable Gate Arrays (FPGAs) attractive for arbitrary-precision arithmetic-heavy workloads such as sparse and mixed-precision DNN inference. However, in modern logic blocks, the hardware adder chain is typically driven only by look-up table (LUT) outputs, preventing adders and LUTs from being used independently and concurrently within a logic element, and reducing the hardware resource utilization efficiency. We propose Double-Duty, a logic block architecture that decouples LUTs and adder chains by augmenting four extra inputs of the logic element to bypass LUTs and directly drive the adders. We model the added circuits at the transistor level and implement full CAD support in open-source tools, including improved arithmetic synthesis to provide a realistic baseline. On a Stratix-10-like architecture, Double-Duty reduces area by 21.6% on Kratos adder-intensive circuits and by 9.3% and 8.2% on the Koios and VTR suites, respectively, improving average area-delay product by 9.7% across all benchmarks with minimal impact on critical path delay. Additionally, we combined Double-Duty with prior arithmetic-oriented optimized architectures, and the fused designs achieve up to 20% area-delay product reduction in geometric mean across multiple benchmarks compared to the baseline.