Arukonda Suresh and K Naresh

Verilog-Based FPGA Realization of KINA: A Karatsuba-Initiated Accelerator for Ring-Binary-LWE Post-Quantum Cryptography

The transition toward post-quantum cryptography requires hardware architectures that can execute lattice-based polynomial arithmetic with low latency and moderate resource cost. This paper presents a Verilog-based realization and evaluation of the Karatsuba Initiated Novel Accelerator (KINA) concept for Ring-Binary Lea...