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Verilog-Based FPGA Realization of KINA: A Karatsuba-Initiated Accelerator for Ring-Binary-LWE Post-Quantum Cryptography

Sep 2026 · International Journal of Advanced Research in Science, Communication and Technology · 0 citations · 6 references

Abstract

The transition toward post-quantum cryptography requires hardware architectures that can execute lattice-based polynomial arithmetic with low latency and moderate resource cost. This paper presents a Verilog-based realization and evaluation of the Karatsuba Initiated Novel Accelerator (KINA) concept for Ring-Binary Learning With Errors based encryption (RBLWE-ENC). The core computation is polynomial multiplication in Z_q/(x^n+1), where one operand is binary and the other is integer-valued. Conventional schoolbook multiplication incurs O(n^2) coefficient operations, while the RBLWE parameter setting is not naturally suited to direct Number Theoretic Transform acceleration. The implemented architecture therefore applies a one-level Karatsuba decomposition that forms three half-size products, T_L, T_H, and T_M, and recombines them through a linear-combination datapath. Circular shift registers support column-wise accumulation, binary point-wise products are realized with simple logic, and the two-bit middle operand is handled by a compact multiplexer-based multiplier. A finite-state controller coordinates clear, load, compute, output, and done phases. For the educational RTL prototype, n=8 and q=256 were used for simulation and synthesis. XSim verification completed successfully with a final visible cipher coefficient of 146 (0x92) and a decoded message bit of 1. RTL elaboration and synthesis confirmed full module connectivity and device mapping, while the reported post-synthesis on-chip power estimate was 0.089 W. The study also analyzes the scalable parallelism factor u, for which multiplication latency decreases from n/2 to n/(2u) cycles at the cost of additional datapath resources. The results demonstrate the functional feasibility of a compact Verilog KINA implementation and provide a practical path toward larger n=256 and n=512 FPGA realizations for lightweight post-quantum security

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