Verilog RTL Design and FPGA Verification of a Karatsuba-Initiated Accelerator for Ring-Binary-LWE Post-Quantum Cryptography
A reproducible Verilog RTL realization and FPGA-oriented verification study of the Karatsuba Initiated Novel Accelerator concept for Ring-Binary Learning With Errors based encryption (RBLWE-ENC) is presented, explicitly distinguishing functional proof-of-concept results from security-strength implementation claims.
Bhaskar Rao Palakurthi, Venkanna Vankudoth, Rajashekar Kakoju et al.
· International Journal of Dru... · 0 citations