Verilog RTL Design and FPGA Verification of a Karatsuba-Initiated Accelerator for Ring-Binary-LWE Post-Quantum Cryptography

Abstract

—Quantum computing motivates hardware implementations of post-quantum cryptography that can deliver predictable latency and low resource cost in embedded and edge platforms. This paper presents a Verilog RTL realization and FPGA-oriented verification study of the Karatsuba Initiated Novel Accelerator (KINA) concept for Ring-Binary Learning With Errors based encryption (RBLWE-ENC). The dominant operation is polynomial multiplication T = B·D mod (x^n + 1), where B is binary and D is integer-valued. Instead of conventional schoolbook multiplication, a controlled one-level Karatsuba decomposition forms three half-size products T_L, T_H and T_M and recombines them through a linear-combination unit. The RTL architecture integrates input processing, circular shift-register banks, pointwise AND/MUX multipliers, accumulation units, a finite-state controller, a phase-dependent output path and a threshold decoder. A compact n=8, q=256 instance is used for functional verification in Vivado before considering scalable n=256 and n=512 parameter sets. The supplied simulation evidence shows successful transaction sequencing, a final cipher output of 0x92 (146), and a decoded message bit of 1. RTL elaboration and synthesis are demonstrated for a Spartan-7-class target, while post-synthesis vectorless power is estimated at 0.089 W. Benchmark data reported for KINA FPGA implementations show that increasing the parallelism factor u decreases multiplication latency from n/2 to n/(2u) cycles and increases throughput at the expense of logic resources. The study therefore provides a reproducible Verilog-centered path from algebraic optimization to FPGA verification for lightweight RBLWE research, while explicitly distinguishing functional proof-of-concept results from security-strength implementation claims.