Author

Ch. Anoosha

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Open access Jul 2026

Optimized 8-bit multiplier architecture using high-order compressors for area-efficient FPGA implementation

These results demonstrate that the proposed compressor-based Wallace Tree multiplier provides an effective balance between area efficiency, power optimization, and computational speed, making it well suited for FPGA-based DSP, image processing, and embedded computing applications.

. KVGowreesrinivas, Ch. Anoosha, SRINIVASANAIDU NALLA · Engineering Research Express · 0 citations