Optimized 8-bit multiplier architecture using high-order compressors for area-efficient FPGA implementation

Abstract

Efficient multiplier architectures are essential for improving the performance of digital signal processing (DSP) and FPGA-based computing systems while minimizing hardware resources, power consumption, and propagation delay. This paper proposes two optimized 8 × 8 Wallace Tree multiplier architectures based on higher-order compressor techniques for FPGA implementation. The proposed architectures employ combinations of 4:3, 5:3, 6:3, 7:3, and 8:4 compressors to simplify partial-product reduction and improve hardware efficiency. Their performance is evaluated in terms of area, power consumption, and propagation delay, and compared with conventional Array, Wallace Tree, and other existing multiplier architectures. Experimental results demonstrate that the proposed Method 1 achieves the best overall performance, providing 40.00% and 41.27% reductions in slice and look-up table (LUT) utilization, respectively, together with 18.95% lower power consumption and 22.90% lower propagation delay than the conventional Array Multiplier. Compared with the Wallace Tree Multiplier, Method 1 further reduces slices, LUT utilization, power consumption, and delay by 8.70%, 12.94%, 9.35%, and 7.53%, respectively. In addition, the proposed methodology achieves greater power savings than comparable existing designs while maintaining lower hardware complexity. These results demonstrate that the proposed compressor-based Wallace Tree multiplier provides an effective balance between area efficiency, power optimization, and computational speed, making it well suited for FPGA-based DSP, image processing, and embedded computing applications.