Open access
Aug 2026
Design and Implementation of a High-Performance RISC-V CPU IP Core for Multiple Cryptographic Algorithms
A hierarchical multiplier architecture consisting of partial-product generation, 4–2 compressor-tree reduction, and a look-ahead adder is developed to improve multiplication throughput and reduce latency compared with conventional Wallace-tree implementations.
Y.-J. Cheng, Cheng-Rui Yin, K.-X. Tang et al.
· Advanced Electromagnetics · 0 citations