Design and Implementation of a High-Performance RISC-V CPU IP Core for Multiple Cryptographic Algorithms

Abstract

To satisfy the low-overhead and high-throughput requirements of embedded computing platforms executing cryptographic workloads, this study presents a high-performance RISC-V CPU IP core compatible with the standard RV32IM architecture. Instead of introducing dedicated cryptographic instructions, the proposed design enhances the execution efficiency of algorithms such as SM3 and SM4 through microarchitectural optimization of arithmetic units. A hierarchical multiplier architecture consisting of partial-product generation, 4–2 compressor-tree reduction, and a look-ahead adder is developed to improve multiplication throughput, while an enhanced radix-4 SRT divider incorporating leading-zero detection, result caching, and dynamic iteration control is proposed to reduce division latency. All modules are implemented in Verilog and integrated into a five-stage RISC-V pipeline. Functional verification is performed using a complete RVM instruction test suite, followed by FPGA-based performance evaluation. Experimental results demonstrate that the multiplier generates 64-bit results within a single clock cycle in 32-bit scenarios, reducing latency by more than 70% compared with conventional Wallace-tree implementations. The proposed architecture provides an efficient computing platform for secure embedded systems and offers implementation references for real-time signal processing, communication security, and electromagnetic information systems.