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Automated repair of High-Level Synthesis (HLS) designs using large language models (LLMs) is an emerging but underexplored problem. While LLM-based repair shows strong results on register-transfer level (RTL) Verilog, the only prior systematic study of HLS logic repair reports just 10.5% correction accuracy for GPT-4,...
This work studies the feasibility of extending to this firmware layer a dictionary- guided, localize-synthesize-validate APR methodology originally developed for RTL repair, and frames these results within a broader research agenda for a unified hardware-to-firmware correctness lifecycle.
Results indicate that dictionary-constrained mutation operators, combined with lightweight simulation-divergence FL, are a practical and competitive approach to automated HDL repair for common bug classes without formal analysis or synthesis dependencies.
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