Open access
Sep 2026
Differential Stochastic Simulated Annealing Processor for Fully Connected 2048-Spin Optimization
A 2,048-spin fully connected annealing processor based on differential stochastic simulated annealing (DSSA) is presented as an architectural design in TSMC 28 nm CMOS with a 3 mm4 mm post-layout area. The processor closes timing at 500 MHz, integrates a 16 Mb SRAM weight memory, and amortizes stochastic noise across 1...
N. Onizawa, Md Mohaimenul Alam, Sean C. Smithson et al.
· IEEE Access · 0 citations