Differential Stochastic Simulated Annealing Processor for Fully Connected 2048-Spin Optimization

Abstract

A 2,048-spin fully connected annealing processor based on differential stochastic simulated annealing (DSSA) is presented as an architectural design in TSMC 28 nm CMOS with a 3 mm4 mm post-layout area. The processor closes timing at 500 MHz, integrates a 16 Mb SRAM weight memory, and amortizes stochastic noise across 16 spins with area-efficient random number generators. DSSA keeps a serialized datapath for density but recomputes interactions only for spins that flip, shrinking the effective workload to the active frontier during each annealing run. Spin-select scheduling, priority-based weight reads, and a temperature controller that skips idle steps accelerate sparse updates without sacrificing full connectivity. Post-layout simulation results show 2.7 ms time-to-solution (TTS) and 0.86 mJ energy-to-solution on 2,000-spin problems at 316 mW (0.15 mW/spin), achieving <inline-formula> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> lower power and <inline-formula> <tex-math notation="LaTeX">$3.5\times $ </tex-math></inline-formula> lower TTS energy than projected prior fully connected annealers. These results demonstrate the potential of the proposed DSSA architecture for large-scale combinatorial optimization hardware under post-layout evaluation.