Author

J. Knechtel

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Preprint Aug 2026

FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?

Can large language models generate not just correct, but fast hardware? This paper investigates the question in financial FPGA design, where 5-10 nanoseconds of latency determines competitive advantage and designs iterate continuously as protocols, strategies, and regulations evolve. FinHardBench, a benchmark of 33 fin...

Weimin Fu, He-Jia Zhang, Ming-Hao Shao et al. · 0 citations

Review Aug 2026

Hardware Design and Security in the Era of Chiplets and LLMs

A unified analysis of attacks on chiplet systems, the integration of Large Language Models into Electronic Design Automation (EDA) flows, and how LLM systems can advance hardware security efforts for modern systems, including chiplets is provided.

J. Knechtel, Ozgur Sinanoglu, Paul V. Gratz et al. · 0 citations