Jie Yu

HEARS: High-Fidelity Emulation for Aging Fault via Scan-Chain Reuse and Flip-Flop Sampling

As semiconductor nodes shrink to 7nm and below, aging-induced delay faults (e.g., NBTI, HCI) increasingly threaten SoC reliability. To optimize resilience, designers require early-stage evaluation of fault impacts; however, traditional Fault Injection (FI) assessments are either bottlenecked by the slow execution of pr...