HEARS: High-Fidelity Emulation for Aging Fault via Scan-Chain Reuse and Flip-Flop Sampling

Abstract

As semiconductor nodes shrink to 7nm and below, aging-induced delay faults (e.g., NBTI, HCI) increasingly threaten SoC reliability. To optimize resilience, designers require early-stage evaluation of fault impacts; however, traditional Fault Injection (FI) assessments are either bottlenecked by the slow execution of precise software simulations or compromised by the "semantic gap" and poor observability of FPGA-based emulation (e.g., Xilinx SEM). This paper presents HEARS, a high-fidelity aging emulation framework that repurposes Design-for-Testability (DFT) scan-chains as both surgical injection mechanisms and high-resolution "internal probes". By leveraging bidirectional shift operations, HEARS achieves deterministic one-to-one mapping between emulation resources and gate-level cells. We introduce an activity-aware adaptive sampling mechanism to focus on cycles with Flip-Flop toggle, where delay violations manifest. Guided by this temporal insight, a Bayesian engine intelligently orchestrates fault injection timing. Crucially, HEARS enables internal state-capture, uncovering latent corruptions invisible to traditional pin-level monitoring. Results show that HEARS achieves a speedup of two to three orders of magnitude over conventional methods while preserving gate-level accuracy.