M. Nagar

Energy and Area-Efficient Custom RISC-V ISA Extensions Using Hybrid 16-Bit Signed Multipliers on FPGAs

This work presents the design and integration of a hybrid 16-bit signed multiplier as a custom (X) instruction set architecture (ISA) extension within a five-stage pipelined RISC-V processor. The proposed RV32IX architecture is synthesized and implemented for the Zynq all programmable system-onchip (APSoC) FPGA platfor...