Energy and Area-Efficient Custom RISC-V ISA Extensions Using Hybrid 16-Bit Signed Multipliers on FPGAs

Abstract

This work presents the design and integration of a hybrid 16-bit signed multiplier as a custom (X) instruction set architecture (ISA) extension within a five-stage pipelined RISC-V processor. The proposed RV32IX architecture is synthesized and implemented for the Zynq all programmable system-onchip (APSoC) FPGA platform, the proposed architecture integrates various signed multipliers to enhance overall performance through custom (X) extensions. The proposed custom (X) ISA extension provides high-speed, energy-efficient v ector multiplication, outperforming standard digital signal processing (DSP)-based extensions on the same platform. Additionally, the performance impacts of several other signed multiplier extensions are meticulously examined for comparison. When integrated with the proposed hybrid 16-bit BR4BD multiplier, the custom RV32IX architecture operates at a maximum usable frequency (MUF) of 73.39 MHz on the Zynq APSoC platform. Experimental results demonstrate that the proposed Booth radix-4 Bewick's Dadda (BR4BD)-based extension achieves a 59.05% reduction in energy consumption (Power-Delay Product, PDP) and a 57.93% reduction in Energy-Delay Product (EDP) compared to state-ofthe-art (SoA) Booth radix-4 compressor-based extensions. The proposed BR4BD extension optimizes FPGA resource density, delivering high-speed execution with up to 1.88% fewer LUTs than SoA softcore alternatives, effectively reduces dependencies on hardware DSP blocks on FPGAs.