Mahesh A. Iyer

FPGA Architectures to Enable Concurrent LUT and Adder Chain Usage

Flexibility and customization make Field-Programmable Gate Arrays (FPGAs) attractive for arbitrary-precision arithmetic-heavy workloads such as sparse and mixed-precision DNN inference. However, in modern logic blocks, the hardware adder chain is typically driven only by look-up table (LUT) outputs, preventing adders a...