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Author

Meenugu Venkateshwarlu

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Conference Jul 2026

Bare-Metal Reconfigurable Accelerators for PicoRV32 RISC-V SoC via AXI-Lite Interface on Zynq-7000

The rise in edge computing, and domain-specific workloads, necessitates the development of hardware acceleration with increased flexibility and lower latency that will be tightly coupled to open-source processor cores. In this paper, we explore the design and bare-metal implementation of a RISC-V SoC comprising a PicoR...

P.anuradha, Vulapala Tejashwi, Meenugu Venkateshwarlu et al. · 0 citations

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