Bare-Metal Reconfigurable Accelerators for PicoRV32 RISC-V SoC via AXI-Lite Interface on Zynq-7000

Abstract

The rise in edge computing, and domain-specific workloads, necessitates the development of hardware acceleration with increased flexibility and lower latency that will be tightly coupled to open-source processor cores. In this paper, we explore the design and bare-metal implementation of a RISC-V SoC comprising a PicoRV32 scalar core and two memory-mapped hardware accelerators: FPSQRT core and a reconfigurable CRC-32 integrity engine. Using a customized three-state AXI4-Lite FSM-based interface, our design effectively separates the acceleration compute latency from that of the bus timings enabling bare-metal firmware to perform its coprocessor computations without OS intervention. Simulation results show performance speed-ups of 1.96x and 9x for the FPSQRT and CRC-32 respectively giving a total speedup of 12x relative to software only. Post-implementation synthesis on the Xilinx Zynq-7000 family FPGA (XC7Z020) shows full timing closure at a clock frequency of 100 MHz with WNS of +7.058 ns. Resource utilization figures are exceptionally low with the design requiring only 5,208 Slice LUT (9.8%), and 11.4% of block RAM with total on-chip power dissipation of 1.694 W. Our hardware-in-the-loop test on the Digilent ZedBoard confirmed the functional accuracy and operational stability with bare-metal operation status confirmed by LED (T21, T22) and a serial console.