Omkar Shirasgaonkar

Congestion-Aware Physical Synthesis and RTL-to-GDSII Implementation of a 90nm RISC-V Execute Pipeline Stage using Cadence Genus and Innovus

This manuscript presents a congestion-aware RTL-to-GDS-II physical synthesis of a RISC-V Execute (EX) pipeline stage at the 90 nm CMOS technology node using Cadence tools- Genus and Innovus. The EX stage integrates a 32-bit ALU, forwarding unit, branch comparator, barrel shifter, operand multiplexers, and EX/MEM pipeli...