Congestion-Aware Physical Synthesis and RTL-to-GDSII Implementation of a 90nm RISC-V Execute Pipeline Stage using Cadence Genus and Innovus

Abstract

This manuscript presents a congestion-aware RTL-to-GDS-II physical synthesis of a RISC-V Execute (EX) pipeline stage at the 90 nm CMOS technology node using Cadence tools- Genus and Innovus. The EX stage integrates a 32-bit ALU, forwarding unit, branch comparator, barrel shifter, operand multiplexers, and EX/MEM pipeline registers, making it inherently prone to routing congestion due to converging datapaths. RTL simulation validates all functional blocks across four stimulus sets. Logic synthesis yields 1363 cells, 8256.26 μm2 area, and 0.625 mW power with a worst-case setup slack of +28 ps. Pre-route congestion prediction reveals hotspots at the ALU and operand MUX regions; mitigation via cell spreading, density screens, and congestion-driven placement re-optimization eliminates all routing overflow. Timing is verified across seven stages—from post-placement through post-route optimization—with final setup slack of +270 ps and hold slack of +55 ps. Postnanoroute verification confirms zero errors and zero warnings. A valid GDS-II output is generated, and a comparison with prior works confirms the novelty and completeness of the proposed methodology.