Hardware hacking competitions have emerged as practical platforms for evaluating security weaknesses in complex System-on-Chip (SoC) designs while promoting security-aware verification and tool development. This paper presents a systematic study of SoC security verification through open-box hardware hacking competition...
Sudipta Paria, Aritra Dasgupta, Raghul Saravanan et al.· 0 citations
This survey presents a comprehensive overview of state-of-the-art hardware fuzzing research, examining how existing hardware fuzzing approaches differ in their fundamental approaches to test generation, simulation infrastructure, mutation strategy, coverage feedback, and bug detection.
This work presents a comprehensive analysis of contemporary hardware fuzzing techniques applied across three major abstraction layers: Instruction Set Architecture (ISA), microarchitecture, and Register-Transfer Level (RTL). Our study examines key factors including input stimulus quality, mutation strategies, feedback...
Alenkruth Krishnan Murali, Raghul Saravanan, D. SaiManojP et al.· 0 citations
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