Fuzzing-Based Verification of Hardware Designs: A Comprehensive Survey

Abstract

As modern hardware systems grow in complexity, traditional pre-silicon verification techniques increasingly struggle to expose deep corner-case behaviors and security-relevant bugs that can persist across the entire lifetime of deployed silicon. In response, hardware fuzzing has emerged as a promising complement to traditional verification approaches, adapting the principles of software fuzzing to systematically explore hardware state spaces and uncover functional bugs, security flaws, and corner-case behaviors in increasingly complex digital designs. Despite growing interest in this field, existing survey efforts remain fragmented, often focusing narrowly on specific hardware targets or fuzzing techniques, and fail to provide a comprehensive overview of the broader hardware fuzzing landscape. Motivated by these gaps, this survey presents a comprehensive overview of state-of-the-art hardware fuzzing research, examining how existing hardware fuzzing approaches differ in their fundamental approaches to test generation, simulation infrastructure, mutation strategy, coverage feedback, and bug detection. We organize prior fuzzing techniques across diverse hardware designs, including processors, Systems-on-Chip (SoCs), Intellectual Property (IP) blocks, and categorize them into five principal categories. We further identify the key trends driving the field forward, analyze the persistent open challenges, and highlight promising emerging directions that will shape the next generation of scalable, security-aware, and practically deployable hardware fuzzing frameworks.