Riyanka Banerjee

Design of a Low-Power Self-Biased Continuous-Time Voltage Comparator in 65nm CMOS Technology

The paper presents a self-biased inverter-based continuous-time voltage comparator, implemented in 65 nm CMOS technology using Low Threshold Voltage (LVT) transistors. The proposed design extends a self-biased single-stage reference architecture, and it does this by reusing a centralized bias network across additional...