Design of a Low-Power Self-Biased Continuous-Time Voltage Comparator in 65nm CMOS Technology

Abstract

The paper presents a self-biased inverter-based continuous-time voltage comparator, implemented in 65 nm CMOS technology using Low Threshold Voltage (LVT) transistors. The proposed design extends a self-biased single-stage reference architecture, and it does this by reusing a centralized bias network across additional cascaded inverter stages, thereby enhancing the open-loop gain and accelerating signal regeneration without introducing additional static current paths. The bias generation network is implemented using diode-connected PMOS and NMOS transistors, establishing the switching threshold near $V_{D D}/2,600 \text{mV}$ to maintain stable operation across the process and temperature variations. At 1.2 V supply, the comparator achieves an open-loop DC gain of $71.73 \text{dB}, \mathrm{a}-3 \text{dB}$ bandwidth of 388 MHz, and a propagation delay of 902.3 ps. The comparator achieves an input-referred noise of $5.4 \mu \mathrm{V}/\sqrt{} \text{Hz}$ and achieves an effective resolution of 11 bits. The average power consumption is $14.58 \mu \mathrm{W}$, and the calculated FoM is 0.0049 fJ /conversion - step, demonstrating competitive energy efficiency compared to recent 65 nm comparator designs. Simulation results show full swing output transitions from ground to supply voltage levels without metastability, validating the proposed architecture for high-speed and low-power mixed-signal applications.