Sio Hang Pun

A 12‐Bit 1‐MS/s 14.96‐ μ W SAR ADC With Improved True Single‐Phase Clock Flip‐Flops

A low‐power 12‐bit 1‐MS/s successive approximation register (SAR) analog‐to‐digital converter (ADC) is presented in this paper. The ADC employs segmented capacitive digital‐to‐analog converter (CDAC) array and improved true single‐phase clock flip‐flops (ITSPCFFs) to reduce power consumption and chip area. The proposed...