A 12‐Bit 1‐MS/s 14.96‐ μ W SAR ADC With Improved True Single‐Phase Clock Flip‐Flops

Abstract

A low‐power 12‐bit 1‐MS/s successive approximation register (SAR) analog‐to‐digital converter (ADC) is presented in this paper. The ADC employs segmented capacitive digital‐to‐analog converter (CDAC) array and improved true single‐phase clock flip‐flops (ITSPCFFs) to reduce power consumption and chip area. The proposed ITSPCFFs effectively block the potential leakage path inherent in conventional true single‐phase clock flip‐flops (TSPCFFs). A kickback noise–suppression technique is adopted in a fully dynamic comparator to improve ADC accuracy without additional power consumption. Fabricated in a 65‐nm CMOS technology, the prototype achieves an ENOB of 10.9 bits and a SNDR of 67.2 dB at a 1‐MS/s sampling rate. Operating at a 1‐V supply voltage, the prototype consumes a total power consumption of 14.96‐ μ W and achieves a FoM of 7.8 fJ/conversion‐step. The proposed SAR ADC features low‐power consumption, high‐energy efficiency, and compact area, making it well suited for systems on chip (SoCs).