Design and Implementation of a 16-Directional 5×5 Sobel Edge Detector on Zynq-7000 FPGA Using AXI-DMA
The edge detection is a crucial procedure in real-time image processing since it allows you to extract features correctly and comprehend the scene. This paper describes a hardware based Sobel edge detector algorithm based on a 16-directional 5 $\times$ 5 kernel implemented on a Zynq-7000 (xc7z020clg400-3) FPGA with various directional gradients to increase clarity of edges relative to the classic 3 $\times$ 3 technique. The hardware/software co-design approach of the system leverages a high-throughput AXI-DMA streaming interface, with hardware taking the heavy load of computationally demanding tasks. The architecture enables the real-time processing continuously with an initiation interval (II) of 1, and thus, the performance is always high. The processing time of a frame is approximately 9.2 ms is achieved and also the hardware resources optimally utilizing 1370 LUTs and 4 BRAM blocks as compared with existing model. The experimental findings reveal a good performance with a balance of accuracy, speed, and efficiency in real-time embedded vision applications with an SSIM of 0.71 and an AUC of 0.80 with respectable error margins.