Jul 2026· 2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)· pp. 1-5· 0 citations· 15 references
Abstract
The edge detection is a crucial procedure in real-time image processing since it allows you to extract features correctly and comprehend the scene. This paper describes a hardware based Sobel edge detector algorithm based on a 16-directional 5 $\times$ 5 kernel implemented on a Zynq-7000 (xc7z020clg400-3) FPGA with various directional gradients to increase clarity of edges relative to the classic 3 $\times$ 3 technique. The hardware/software co-design approach of the system leverages a high-throughput AXI-DMA streaming interface, with hardware taking the heavy load of computationally demanding tasks. The architecture enables the real-time processing continuously with an initiation interval (II) of 1, and thus, the performance is always high. The processing time of a frame is approximately 9.2 ms is achieved and also the hardware resources optimally utilizing 1370 LUTs and 4 BRAM blocks as compared with existing model. The experimental findings reveal a good performance with a balance of accuracy, speed, and efficiency in real-time embedded vision applications with an SSIM of 0.71 and an AUC of 0.80 with respectable error margins.
In an effort to mitigate processing delays and latency in the traditional edge detection in the vision based systems such as robotics and surveillance platforms, this paper attempts to introduce an FPGA-based 3×3 convolution accelerator. The proposed architecture employs a multiply-accumulate (MAC) unit and fixed-point...
Aysha Pareekutty, R. Megalingam· International Conference on...· 0 citations
The proposed architecture achieves sub-linear resource scaling, with less than 20% increase in resource utilization and less than 20% reduction in speed and power when handling a 56-fold increase in pixel count, leveraging the advantages of modern heterogeneous FPGA architecture.
Isha Gupta, D. P. Kaur, Deepali Gupta· Journal of Visualized Experi...· 0 citations
Image scaling serves as a critical performance bottleneck in real-time video pipelines powering multi-resolution embedded display systems. The design integrates a dual ping-pong line buffer architecture to deliver four pixels per clock cycle, paired with a digital differential analyzer (DDA) for precise sub-pixel coord...
Sirui Wang· Computers and artificial int...· 0 citations
This paper presents an FPGA feasibility study of two digital processing blocks for a future real-time Visible Light Positioning (VLP) receiver: a Sliding Discrete Fourier Transform (SDFT) stage for carrier-magnitude extraction and a hardware-optimized Multi-Layer Perceptron (MLP) inference engine for coordinate estimat...
Randy Lozada Domínguez, Aran White, Jianming Tang et al.· Electronics· 0 citations
A K=16 piecewise-linear approximation of the Gaussian range kernel has been used to avoid exponential evaluation hardware and reduced coefficient storage by a factor of 32 and a piecewise approximate bilateral filter structure is proposed and realised on the Xilinx Zynq XC7Z020 System-on-Chip (SoC) in this paper.
Xin-Yu Liu· European Conference on Elect...· 0 citations
A combined hardware-andalgorithm design that pairs a carefully regularized binarized neural network (BNN) with a compact, variable-precision FPGA processor to enable accurate, real-time object detection without relying on off-chip memory is proposed.
M. Kanthi, Ragala Karthik· International Journal of AI...· 0 citations
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