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Thithikshaa S

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Conference Aug 2026

An Area-Efficient 8-Stage Out-Of-Order Risc-V Core with Integrated Floating Point for Embedded FPGA Platforms

An eight-stage out-of-order superscalar RISC-V core with integrated single precision floating point is presented, targeted at embedded FPGA deployment where logic area is constrained but tolerance to long latency floating point operations is still desirable. Dynamic scheduling is realised through a renaming front end b...

Sujal Yatin Vaidya, Thithikshaa S, Sowmyashree Mukunda et al. · 0 citations

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